The LVTSCR, originally developed by Texas Instruments, has found widespread application as a control device, especially in electrostatic discharge (ESD) protection. A cross-section through a typical LVTSCR is shown in FIG. 1, which shows a p+ well contact 102, source 104, polygate 106, floating n+ drain 108, p+ drain 110, and n+ drain contact 112. To avoid the two n− regions 108, 112 simply acting as drains of a NMOS transistor, the p+ drain 110 is isolated from the p-substrate 120 by a n-well 122, the structure being controlled by the primary snapback of the NMOS structure which is dictated by the breakdown voltage that is determined by the electric field under the polygate 106.
The problem with the LVTSCR 100 is that it has a rather high breakdown voltage, thus having a high triggering voltage. Also, a cascaded structure is typically required when using a LVTSCR as overvoltage clamp where the voltage typically exceeds the maximum gate voltage.
The present invention addresses the above shortcomings of the LVTSCR structure of FIG. 1.